x86 vs ARM Memory Ordering
Discussions center on differences in memory models between x86 (strong ordering, TSO) and ARM (relaxed, requiring barriers), including store buffers, reordering, compiler optimizations, and the need for atomics or fences for correct concurrency.
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X64 has stronger guarantees than that without barriers doesn't it?
A lot of it has to do with the stricter requirements on ordering of memory operations on x86 right?
Don't forget ARM's more relaxed memory model vs. x86's TSO.
It sounds like you have software in your stack which assumes a strong memory model.
Is that lot true on x86? I thought it's (fairly) strict memory ordering meant you didn't have acquire type thing?
The code is missing a memory barrier. x86 has a strongly ordered memory model, but writes can reside in the store buffer and take a long time before becoming visible to other parts of the system.
Where did you see the article claim it was a memory barrier?
He means x86 doesn't reorder memory store order with other stores or loads with other loads, etc.See: https://en.wikipedia.org/wiki/Memory_ordering#In_symmetric_m...
CPU memory model and atomics support is what matters here. Dalvik or ART are unlikely to have anything to do with it, as long as they provide access.
This guy pretend that x86 is strongly ordered, while it is not...