Verilog/VHDL Alternatives
Discussions compare traditional hardware description languages like Verilog and VHDL to modern alternatives such as Chisel, nmigen, and Clash, focusing on their design flaws, usability, and suitability for FPGA/ASIC development.
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Does this improve on languages like VHDL and Verilog?
You should try out Chisel. I learned and used VHDL first, but after switching to Chisel I realized it was much better designed and avoided many of the footguns you'll likely encounter with Verilog or VHDL. And in general, it is a joy to work with.
Shouldn't Verilog/VHDL be on top? :)
The problem is that Verilog/VHDL isn't a "programming language" in the sense that C, Lisp, Haskell, or Python are programming languages. So approaching them with a programming language mindset is asking for a lot of pain and misunderstanding.HDLs like Verilog and VHDL describe digital circuits, not algorithms and instructions for manipulating data. If C code is akin to instructions for getting to a grocery store and shopping for vegetables, HDL code is describing the bluep
VHDL and Verilog on FPGAs/ASIC is parallel - we don't think serially at all!
Please don't use VHDL. Use verilog, as a great cycle accurate FOSS simulator/compiler exists for it (Verilator).
Is there anything like this for ASIC design / Verilog?
Would be good to see a comparison to Verilog
True. You're pretty much stuck with verilog at that point.
Do you focus on HDL's, ie. Verilog or SystemC?