SSA in Compilers

This cluster focuses on discussions about Static Single Assignment (SSA) form in compiler intermediate representations (IR), particularly LLVM, including its use for optimizations, transformations, and comparisons to existing compiler techniques.

➡️ Stable 0.9x Programming Languages
2,815
Comments
19
Years Active
5
Top Authors
#4148
Topic ID

Activity Over Time

2008
5
2009
17
2010
29
2011
52
2012
46
2013
84
2014
81
2015
212
2016
222
2017
210
2018
146
2019
182
2020
228
2021
196
2022
210
2023
234
2024
268
2025
375
2026
20

Keywords

e.g optimizingLLVMIR.pdf CPU ssa.pdf IR discordapp.com SSA www.cs THE lang.org ir compiler llvm optimizations compilers assignment code compilation ast register

Sample Comments

fintler • Mar 2, 2016 • View on HN

Just a guess: it's probably static single assignment for the IR.https://www.cs.cmu.edu/~fp/courses/15411-f08/lectures/09-ssa...

avadodin • Oct 31, 2025 • View on HN

We're all already doing this as the compiler turns everything into SSA form, silly goose.

grumpyprole • May 22, 2024 • View on HN

It's painful for the compiler too, it has to turn the parents imperative code into SSA (essentially A-normal form) so it can optimise it!

raverbashing • Jun 24, 2015 • View on HN

Not really, simplifying simple operations (like multiply by a constant) is pretty much Compilers 101 / Dragon Book kind of stuff

adrianN • Dec 27, 2019 • View on HN

Are there production compilers who don't do SSA nowadays?

oconnor663 • Mar 31, 2018 • View on HN

Doesn't the LLVM backend make tons of similar optimizations under the hood?

astrange • May 13, 2023 • View on HN

You'd need to reimplement LLVM code generation and all. These optimizations only work in that part of the compilation process; do it on your own IR and after lowering to LLVM you'll still want to do it again.

amelius • May 1, 2025 • View on HN

Is someone working on similar ideas for compiler back-ends?

tylerhou • May 16, 2025 • View on HN

You should look at supercompilation.

dist1ll • Nov 19, 2025 • View on HN

Sure, these days I'm mostly working on a few compilers. Let's say I want to make a fixed-size SSA IR. Each instruction has an opcode and two operands (which are essentially pointers to other instructions). The IR is populated in one phase, and then lowered in the next. During lowering I run a few peephole and code motion optimizations on the IR, and then do regalloc + asm codegen. During that pass the IR is mutated and indices are invalidated/updated. The important thing is that t