RISC-V ISA Debate

RISC-V has the C extension (compressed opcodes, similar to Thumb-2) and code density then is comparable to x86 which is the main CISC in use these days.

It's RISC-V that's MIPS-ish, not the other way around.

What does RISC-V do computationally better than the current ARM variants?

How does this compare to RISC-V?

isn't that why RISC exists?

It's not exactly RISC VS CISC.Maybe SISC - "Simplified" instruction set computing, perhaps. ARM isn't exactly super complicated in this particular aspect (it is elsewhere), but in this case the designers basically chose to make branches simpler at the expense of code that needs to check overflows (or flags more generally)RISC-V was born partly out of a desire for a teaching ISA, also, so simplicity is a boon in that context too.

Because it's RISC under the hood

RISCV is an instruction set, but you compare ASICsIf qualcomm changes instruction decoding over you’ll likely see a dramatic difference

Seriously? You weren’t aware of this?The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-Vhttps://people.eecs.berkeley.edu/~krste/papers/EECS-2016-130...

There was an article on HN where someone called RISC-V a bit too RISCy. ARM has instructions that combine things that are commonly combined, which increases code density and requires fewer instruction decoders (as well as possibly instruction combine logic if there are micro/macro-ops) for the same performance.