Chip Size Limitations

None. The problem is the traces and the kind of signal that has to travel on the traces, not the chips.

Probably cost and performance. When you string more of these chips together, the propagation delay increases which means your clock speed must be inversely.

Just speculating, but I'd have to assume it has to do with VLSI design and reducing complexity of how wires are laid out on the die in order to increase efficiency.

That would be colossally inefficient - essentially the size of the chip means that electrons would be taking multiple cycles to get from one side to the other. The solution would be localizing processing into distinct processing units on the one die. At the point you’ve reinvented multiple cores and it starts becoming cost effective to split them into separate chips to improve yields :)

I have the same question. My first guess would be it was due to the reality of using the limited space and design process. Note the mention in the article about asynchronous logic and hand-wired gates. It probably seemed a better trade-off to keep the circuit as simple as possible if it would work fine and out of the box for a majority of the cases.

Can you elaborate on the "Wider processors are harder to clock faster" part?

It is not wrong, it is rather correct. Speed of propagation in semiconductor materials is at most a third of speed of light in vacuum. So the distance travelled is rather limited for a signal. Also, a signal might have to traverse a few transistors or gates, so frequency in the 3GHz range does really limit processor sizes to the order of millimeters. You already said how to get around it: Pipelines, that limits the area a signal has to propagate. Also, one has to take care to make signals arrive

Whilst it's true that modern chips have problems with routing clocks, that's not really a limiting factor in chip size. You split the design into clock regions and have clock crossing logic. There's obvious ways this happens - multi-core designs have different clocks for different cores for example. That's not really the limiting factor for chip size.

Only a little, one big limitation in chips is RC wire delays (the distributed capacitance along a wire needs to be charged/discharged for a signal change to pass) - due to edge effects capacitance doesn't scale with the area of the wire - but R does (inversely so wires have gotten slower) - so as chips have got denser wires have not got faster at the same rate, when I first started building chips we mostly only cared about gate capacitances - now RC delays are a big deal - if R went to

Wouldn't smaller chips make the problem worse?